1. Technical Field
The present invention relates to a variable delay circuit to be implemented to an integrated circuit, a recording medium storing therein a program that operates a computer as a logic verification apparatus that conducts logic verification directed to an integrated circuit to which a variable delay circuit is implemented, a logic verification method for device data with use of the variable delay circuit, and an electronic device using the variable delay circuit.
2. Related Art
Recently, computer-aided designing (CAD) has been adopted in an integrated circuit constituted by numerous circuit devices such as transistors, since it is difficult to design all the concrete circuit structures of such an integrated circuit manually. The development stage that uses the CAD is performed as follows; using so-called hardware description language based on the decided specification, abstract circuit data is defined in accordance with a function of an integrated circuit to be developed; a logic circuit is generated by performing logic synthesis or the like based on the defined circuit data; and the concrete circuit structure is thereafter defined to be implemented onto a chip (e.g. see the Japanese Patent Application Publication No. H10-283388.)
In an integrated circuit manufactured by undergoing such a design stage, verification operations both in logic level and in actual operation level are generally performed during the manufacturing stage. For example, logic verification is conducted using a low-speed inspection apparatus in the wafer level stage thereby expelling defective items, and the actual operation verification is performed in the stage after the packaging of chips is completed, so that only products judged as non-defective are shipped.
In the stage of actually forming designed circuits onto a semiconductor substrate, it is not easy to fully reproduce the electric characteristics of the designed circuit structure, due to process variations and the like. There are cases where the characteristic is different between the designed circuit and the implemented circuit. It will cause no problem in practical sense if such a characteristic difference is minor. However, in such sections as operating in high speed, there are cases where the operations are adversely affected due to a difference in time delay caused by wiring length variations and the like.
So as to counter this problem, there have been already proposed integrated circuits incorporating therein a variable delay circuit for assigning a variable time delay for absorbing fluctuation in time delay attributable to process variations and the like and for realizing characteristics as designed. By adjusting the time delay with use of such a variable delay circuit, it becomes possible to absorb time delay fluctuation attributable to process variations and the like, and further to improve yield of the integrated circuits.
However, an integrated circuit incorporating therein a conventional variable delay circuit has a problem that logic verification by means of a low-speed inspection apparatus is difficult. This problem is detailed as follows.
FIG. 9 is a schematic diagram showing one example of a circuit structure that uses a conventional variable delay circuit The circuit illustrated in FIG. 9 is composed of a variable delay circuit 101, a flip-flop circuits 102 and 103, and delay circuits 104 and 105. The following problem arises when low-speed verification is performed on such a circuit using a low-speed inspection apparatus.
Conventional variable delay circuits cannot define the time delay at a certain value even in the low-speed verification because the time delay amount to be assigned is variable. Accordingly, when for example such a variable delay circuit is adopted in the circuit structure as shown in FIG. 9, it is not certain whether it is possible to provide a sufficient hold time for holding the data to be inputted to the flip-flop circuit 102 that is positioned in the later stage. Accordingly, when a circuit structure as shown in FIG. 9 is realized using a conventional variable delay circuit, sometimes low-speed verification may find it a defective item even if the flip-flop circuit 102 itself does not have any problem and can operate without trouble if using a variable delay circuit after adjustment of the time delay, which means deterioration in verification accuracy.
This also applies to logic verification in the designing stage. It is difficult to adopt integrated circuits incorporating therein conventional variable delay circuits to a normal logic design environment, and the number of processes required for analogue verification greatly increases.